cystech electronics corp. spec. no. : c854k3 issued date : 2012.10.08 revised date : page no. : 1/6 btb1236ak3 cystek product specification silicon pnp epitaxial planar transistor btb1236ak3 description ? high bv ceo ? high current capability ? pb-free lead plating package symbol outline to-92l btb1236ak3 c collector e emitter b base absolute maximum ratings (ta=25 c) parameter symbol limits unit collector-base voltage v cbo -180 v collector-emitter voltage v ceo -160 v emitter-base voltage v ebo -7 v collector current (dc) i c -1.5 a collector current (pulse) i cp -3 a base current i b 0.5 a collector power dissipation p c 900 mw junction temperature tj 150 c storage temperature tstg -55~+150 c
cystech electronics corp. spec. no. : c854k3 issued date : 2012.10.08 revised date : page no. : 2/6 btb1236ak3 cystek product specification characteristics (ta=25 c) symbol min. typ. max. unit test conditions bv cbo -180 - - v i c =-50 a, i e =0 bv ceo -160 - - v i c =-1ma, i b =0 bv ebo -7 - - v i e =-50 a, i c =0 i cbo - - -1 a v cb =-160v, i e =0 i ebo - - -1 a v eb =-5v, i c =0 *v ce(sat) - - -0.3 v i c =-500ma, i b =-50ma *v ce(sat) - - -0.6 v i c =-1a, i b =-100ma *v be(on) -0.45 - -0.75 v v ce =-5v, i c =-5ma h fe 1 100 - 320 - v ce =-5v, i c =-200ma h fe 2 30 - - - v ce =-5v, i c =-500ma f t - 180 - mhz v ce =-5v, i c =-150ma cob - 24 - pf v cb =-10v, i e =0, f=1mhz *pulse test: pulse width 380s, duty cycle 2% classification of h fe 1 rank o y range 100~200 160~320 ordering information device hfe rank package shipping BTB1236AK3-O-BK-S o to-92l (pb-free lead plating) 500 pcs / bag, 10 bags/box, 10 boxes/carton btb1236ak3-y-bk-s y to-92l (pb-free lead plating) 500 pcs / bag, 10 bags/box, 10 boxes/carton btb1236ak3-o-tb-s o to-92l (pb-free lead plating) 2000 pcs / tape & box btb1236ak3-y-tb-s y to-92l (pb-free lead plating) 2000 pcs / tape & box
cystech electronics corp. spec. no. : c854k3 issued date : 2012.10.08 revised date : page no. : 3/6 btb1236ak3 cystek product specification typical characteristics current gain vs collector current 10 100 1000 1 10 100 1000 10000 collector current---ic(ma) current gain---hfe vce=1v vce=2v vce=5v saturation voltage vs collector current 10 100 1000 1 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) vcesat@ic=10ib vcesat@ic=50ib saturation voltage vs collector current 100 1000 1 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) vbesat@ic=10ib vbesat@ic=50ib on voltage vs collector current 100 1000 1 10 100 1000 10000 collector current---ic(ma) on voltage---vbeon(mv) capacitance vs reverse-biased voltage 10 100 1000 0.1 1 10 100 reverse-biased voltage---vr(v) capacitance--(pf) power derating curve 0 100 200 300 400 500 600 700 800 900 1000 0 50 100 150 200 ambient temperature---ta() power dissipation---pd(mw)
cystech electronics corp. spec. no. : c854k3 issued date : 2012.10.08 revised date : page no. : 4/6 btb1236ak3 cystek product specification to-92l taping outline millimeters dim item min. max. a1 component body width 4.70 5.10 a component body height 7.80 8.20 t component body thickness 3.70 4.10 d lead wire diameter 0.40 0.50 d1 lead wire diameter 1 0.62 0.78 p pitch of component 12.40 13.00 p0 feed hole pitch 12.50 12.90 p2 hole center to component center 6.05 6.65 f1, f2 lead to lead distance 2.20 2.80 h component alignment, f-r -1.00 1.00 w tape width 17.50 19.00 w0 hole down tape width 5.50 6.50 w1 hole position 8.50 9.50 w2 hole down tape position - 1.00 h height of component fr om tape center 19.00 21.00 h0 lead wire clinch height 15.50 16.50 l1 lead wire (tape portion) 2.50 - d0 feed hole diameter 3.80 4.20 t1 taped lead thickness 0.35 0.45 t2 carrier tape thickness 0.15 0.25 p1 position of hole 3.55 4.15 p component alignment -1.00 1.00
cystech electronics corp. spec. no. : c854k3 issued date : 2012.10.08 revised date : page no. : 5/6 btb1236ak3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c854k3 issued date : 2012.10.08 revised date : page no. : 6/6 btb1236ak3 cystek product specification to-92l dimension *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.146 0.161 3.700 4.100 e 0.307 0.323 7.800 8.200 a1 0.050 0.062 1.280 1.580 e *0.05 *1.270 b 0.014 0.022 0.350 0.550 e1 0.096 0.104 2.440 2.640 b1 0.024 0.031 0.600 0.800 l 0.543 0.559 13.800 14.200 c 0.014 0.018 0.350 0.450 ? - 0.063 - 1.600 d 0.185 0.201 4.700 5.100 h 0.000 0.012 0.000 0.300 d1 0.157 - 4.000 - notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . marking: s t yle: pin 1.emitter 2.colle ctor 3.ba se 3-l ead t o -9 2l plasti c pa ckage cys t ek pa ck a g e code: k3 product name date code: y ear+month y ear: 7 2007, 8 20 08 month: 1 1, 2 2, ??? , 9 9, a 10, b 11 , c 12 b1236
|
